Compared to wire bonding technique, flip-chip package technique introduced by IBM Inc. in early 1960 allows semiconductor chips and chip carriers to be electrical connected via solder bumps rather than gold wires, which enhances package density and lowers package size. Meanwhile, this flip-chip technique does not require the longer-length gold wires, thus improving electrical performance.
In current flip-chip technique, electrode pads are disposed on an electrical surface with a surface mounted device such as an semiconductor Integrated Circuit (IC) chip, and corresponding contact solder pads are formed on an organic circuit board, so as to dispose solder bumps or other conductive adhesive materials between the semiconductor chip and circuit board, allowing the chip to be situated on the circuit board with its electrical contact surface facing downward. The solder bumps or conductive adhesive materials provide electrical Input/Output (I/O) and mechanical connection between the chip and the circuit board. A method of forming conductive bumps on a circuit board via electroplating is described below in conjunction with the drawings.
FIGS. 1A to 1H are cross-sectional schematic diagrams depicting a structure corresponding to a traditional method of forming conductive bumps on a circuit board. As shown, a first conductive layer 12 (as shown in FIG. 1A) is formed on an insulating layer 11 of a surface of the circuit board; then a first resist layer 13 is formed (as shown in FIG. 1B) on the first conductive layer 12; a plurality of openings 130 are then formed on the first resist layer 13 to expose the first conductive layer 12; electroplating is performed thereafter so as to form electrical connecting pads 140 (as shown in FIG. 1C) on the first conductive layer 12 within the first openings 130; then the first resist layer 13 is stripped away and etching is performed to remove part of the first conductive layer 12 that was covered by the first resist layer 13 (as shown in FIG. 1D).
The above-described steps that allow electrical connecting pads 140 to be formed on a surface of the circuit board complete a required first stage of the whole process. Thereafter, a solder mask 15 is formed on the circuit board formed with electrical connecting pads 140 in order to protect the circuit board from environmental pollution and/or damage. Then, a plurality of second openings 150 can be formed on the solder mask 15 via steps such as exposure and development, such that the electrical connecting pads 140 are exposed through the second openings 150 of the solder mask 15 (as shown in FIG. 1E). Furthermore, a second conductive layer 16 is formed on the solder mask 15 and its second openings 150 as electrical current conductive path for the subsequent electroplating process. A second resist layer 17 is formed on the second conductive layer 16 and a plurality of third openings 170 are formed on the second resist layer 17 to expose part of the second conductive layer 16 (as shown in FIG. 1F). Thereafter, electroplating is performed again, so as to form solder materials 18 on the second conductive layer 16 within the third openings 170 (as shown in FIG. 1G). The second resist layer 17 is then stripped away and etching is performed to remove the second conductive layer 16 that was covered by the second resist layer 17, such that reflow is performed on the solder materials 18 to form solder bumps (not shown).
As can be seen from the above steps, the solder mask and the second resist layer respectively gone through exposure and development during patterning in order to form the second openings and the third openings, thereby forming conductive bumps within the third openings. Since that patterning (exposure and development etc.) are performed twice to form the second openings and the third openings, the size of the third openings are limited by that of the second openings. As a result, the pitch between the conductive bumps cannot be minimized, that is, the size of the openings of the solder mask (solder proof layer) and of the second resist layer (electroplating-resist layer) is mainly formed via exposure and development. Moreover, fine alignment is required, but the alignment precision of a standard machine is approximately 20 μm-30 μm, thus the openings of the second resist layer cannot be easily aligned to the center of the openings of the solder mask. Thus, the size of the openings is forced to be enlarged to reduce alignment difficulty and precision. Enlarging the size of the openings of the second resist layer compromises the fine pitch requirement of the electrical connecting pads. Thus, the electroplating process is not able to effectively form fine pitched conductive bumps on the electrical connecting pads. If fine pitched conductive bumps are required, then the alignment precision of the solder mask and the resist layer must be increased, this complicates the process, increases the time required as well as the alignment difficulty.
Furthermore, since solder materials are directly formed on the electrical connecting pads in the openings of the solder mask, the height of the solder materials on the electrical connecting pads are not easily controlled to be uniform, affecting the subsequent process reliability when the circuit board is electrically connected to external electronic components.